1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas, such as gate electrodes and drain and source regions, are connected to the metallization system of the semiconductor device on the basis of contact elements.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. However, the continuing scaling of feature sizes involves great efforts in redesigning process techniques and developing new process strategies and tools to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, a large number of field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain terminal and a source terminal.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, memory devices and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor element but the electrical performance of the complex wiring network, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the individual circuit elements and of the various stacked metallization layers.
Furthermore, to establish a connection of the circuit elements with the metallization layers, an appropriate vertical contact structure is provided, which connects to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and to a respective metal line in the first metallization layer. The contact structure may comprise contact elements or contact plugs formed in an interlayer dielectric material that encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with the density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level may have to be provided with appropriate critical dimensions on the same order of magnitude. The contact elements may typically represent plugs, trenches and the like which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, the interlayer dielectric material may be formed first and may be patterned so as to receive contact openings, which may extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. For this purpose, openings of very different depth may have to be formed in the interlayer dielectric material in order to connect to gate electrode structures or any other conductive lines formed above the semiconductor layer, while other contact openings have to extend down to the semiconductor layer, i.e., any contact areas formed therein. In particular, in densely packed device regions, the lateral size of the drain and source areas, and thus the available area for the contact regions, may be 100 nm and less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy, while the difference in etch depth may additionally contribute to the overall complexity of the patterning process. After exposing the contact areas, frequently provided in the form of metal silicide regions, a barrier material is frequently provided, for instance in the form of a material system including titanium and titanium nitride, wherein the titanium material may provide the required adhesion characteristics, while the titanium nitride material may preserve integrity of the interlayer dielectric material during the subsequent deposition of the tungsten material, which may be accomplished on the basis of sophisticated chemical vapor deposition (CVD) techniques in which a direct contact between silicon dioxide-based material and the deposition ambient for depositing the tungsten material is to be avoided. Typically, the actual deposition of the tungsten material may be preceded by the deposition of a nucleation layer based on tungsten, which may be accomplished by a dedicated deposition step, after which the actual fill material may be provided. After the deposition of these materials, any excess material may be removed, for instance by chemical mechanical polishing (CMP), thereby forming the isolated contact elements in the interlayer dielectric material. Although the process sequence for patterning the contact openings and filling these openings with barrier materials and tungsten results in contact elements having a desired contact resistivity for semiconductor devices with critical dimensions of 50 nm, a further reduction of the size of the transistors may result in an increased contact resistivity, which may no longer be compatible with the device requirements. That is, upon further device scaling, the increased contact resistivity, which may result from conventional tungsten-based contact regimes, may represent a limiting factor of the operating speed of the integrated circuits, thereby at least partially offsetting many advantages obtained by the further reduction of the critical dimensions in the device level.
For these reasons, other deposition strategies have been developed for filling high aspect ratio contact openings, such as electrochemical deposition and the like. Although in some of these approaches specific conductive barrier materials, such as titanium nitride, tantalum nitride and the like, may not be required, which thus may provide superior overall conductivity of the resulting contact elements, upon further device scaling, deposition-related irregularities, such as voids and the like, may significantly increase the overall contact resistance, as will be explained in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 including a plurality of semiconductor-based circuit elements 150, which are formed in and above a semiconductor layer 102. The semiconductor layer 102 is formed above a substrate 101, such as a semiconductor material and the like. For example, the circuit elements 150 may represent field effect transistors comprising a gate electrode structure 151, which has any appropriate configuration in accordance with the overall device requirements. The gate electrode structure 151 comprises a contact area 155, which may be a portion of an electrode material and the like. Furthermore, the transistors 150 comprise drain and source regions 153 formed in a corresponding active region 102A, which represents a portion of the semiconductor layer 102 in which the PN junctions and thus dopant profiles of one or more transistors, such as the transistors 150, are formed. The drain and source regions 153 typically comprise a contact area 154, for instance in the form of metal silicide regions and the like. Moreover, the transistors 150 are embedded in a dielectric material 110, which is also referred to hereinafter as an interlayer dielectric material which thus represents a dielectric material formed so as to passivate the transistors 150 and any other semiconductor-based circuit elements and separate these circuit elements from a metallization system (not shown) that is to be formed above the interlayer dielectric material 110. As illustrated, the interlayer dielectric material 110 may comprise two or more different materials, such as a layer 111, for instance provided in the form of a silicon nitride material, followed by a further layer 112, such as a silicon dioxide material. Furthermore, contact elements 120A, 120B are formed in the interlayer dielectric material 110 and comprise an appropriate conductive material 122, such as tungsten, cobalt and the like, wherein, frequently, as discussed above, an activation material 121 is formed on sidewalls of the contact elements 120A, 120B and a bottom thereof in order to initiate, for instance, the electrochemical deposition of the actual fill material 122. Furthermore, as illustrated, the contact elements 120A, 120B extend to the contact areas 155, 154, respectively, and thus may extend to different height levels in the device 100, which is to be understood as the “vertical” distance of the bottom of the contact openings 120A, 120B from any appropriate reference plane, such as the interface formed between the semiconductor layer 102 and the substrate 101. In this sense, the height level of the bottom of the contact element 120B is less than the height level of the bottom of the contact opening 120A.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of established process strategies in which the active region 102A and the circuit elements 150, for instance in the form of field effect transistors, may be fabricated in accordance with sophisticated process strategies. For example, the fabrication of the gate electrode structures 151 represents a very critical process phase, since, in sophisticated applications, a gate length 151L may be 50 nm and significantly less, thereby requiring sophisticated lithography and etch strategies. Moreover, complex material systems may be used, for instance in the form of high-k dielectric materials for a gate dielectric material, in combination with metal-containing electrode materials, depending on the overall device requirements. Similarly, the dopant profiles of the drain and source regions 153 may require appropriate manufacturing strategies. At any appropriate manufacturing stage prior to or after completing transistors 150 as shown in FIG. 1a, at least a portion of the interlayer dielectric material 110 is formed. For example, the layer 111 may be deposited on the basis of plasma assisted CVD techniques, followed by the deposition of the material 112, for instance using sub-atmospheric CVD and the like. Thereafter, the resulting surface topography is typically planarized, for instance by CMP, to provide superior process conditions for patterning the interlayer dielectric material 110 in order to form corresponding contact openings therein. For this purpose, any sophisticated process strategies are applied, for instance using hard mask materials and the like. Thereafter, the activation layer 121 or a conductive barrier layer is deposited, for instance by CVD, sputter deposition and the like, thereby preparing the device 100 for a subsequent deposition of the actual fill metal 122. As discussed above, the fill material 122 has to be filled into the contact openings having at least one lateral dimension that may be comparable to the critical dimensions of the transistors 150, thereby requiring sophisticated deposition techniques. However, certain deposition-related irregularities, for instance in the form of seam and voids 123, may nevertheless be created, even if highly non-conformal deposition recipes are applied, for instance by using electro-chemical deposition techniques. After filling in the conductive contact metal 122 and after removing any excess material, for instance by CMP and the like, thereby also removing any portions of the activation or barrier layer 121 from horizontal areas of the interlayer dielectric material 110, the seam voids 123 may contribute to further non-uniformities during the further processing and may also cause a significantly increased contact resistance, which may contribute to reduced overall device performance.
FIG. 1b schematically illustrates the semiconductor device 100 in a manufacturing stage in which the contact metal 122 is deposited so as to fill contact openings 110A, 110B based on deposition recipes in which a superior “bottom to top” fill behavior may be achieved in an attempt to reduce or avoid corresponding seams or voids, as, for instance, shown in FIG. 1a in the form of the voids 123. In this case, however, a significant risk of creating voids 124 at the upper portion of the contact openings 110A, 110B may exist, since, at a final phase of the deposition process, the growth of the material 122 at the top of the openings 110A, 110B may result in a “pinch off” of the deposition species, thereby forming the voids 124. Consequently, upon removing any excess material of the layer 122, the voids 124 may at least partially remain in the resulting contact elements and may thus contribute to further non-uniformities during the further processing and may also reduce the overall conductivity.
The present disclosure is directed to various devices and methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.